1. Field of the Invention
The present invention relates generally to the field of a semiconductor device, and more particularly to a non-planar semiconductor device with fin structures and a fabrication method thereof.
2. Description of the Prior Art
With the trend in the industry of scaling down the size of metal oxide semiconductor transistors (MOS), three-dimensional or non-planar transistor technology such as fin field effect transistor technology (Fin FET) has been developed to replace planar MOS transistors. The three-dimensional structure of a fin FET increases the overlapping area between the gate and the fin-shaped structure of the silicon substrate, so that the channel region is more effectively controlled. The drain-induced barrier lowering (DIBL) effect and short channel effect (SCE) are therefore reduced. The channel region is also longer under the same gate length, which increases the current between the source and the drain.
In order to further improve the device's performance, a strained-silicon technology has also been developed. The main principle is that strains are applied to predetermined regions within the semiconductor device, which in turn make the semiconductor device work better by enabling charge carriers, such as electrons or holes, to pass through the lattice of the channel more easily. One main technology disposes epitaxial structures with lattice constants different from that of the crystal silicon in the source/drain regions of the semiconductor devices. The epitaxial structures are preferably composed of silicon germanium (SiGe) or carbon-doped silicon (SiC), which have lattice constants different from that of the crystal silicon. Since the epitaxial structures have lattice constants which are larger or smaller than that of the crystal silicon, carrier channel regions adjacent to the epitaxial structures can sense external stress, and both the lattice structure and the band structure within these regions are thereby altered. As a result, the carrier mobility and the performances of the corresponding semiconductor devices are improved.
With the continued decrease in the size and dimensions of semiconductor devices, however, there are newly generated technological problems that need to be overcome, even with the adoption of the non-planar transistor with raised source/drain regions. How to effectively eliminate these defects and improve the performance of the semiconductor devices are important issues in this field.